CKSEL=RISING_EDGES_ON_INPU, UNIFY=THE_SCT_OPERATES_AS, CLKMODE=THE_BUS_CLOCK_CLOCKS
SCT configuration register
| UNIFY | SCT operation 0 (THE_SCT_OPERATES_AS): The SCT operates as two 16-bit counters named L and H. 1 (THE_SCT_OPERATES_AS): The SCT operates as a unified 32-bit counter. |
| CLKMODE | SCT clock mode 0 (THE_BUS_CLOCK_CLOCKS): The bus clock clocks the SCT and prescalers. 1 (THE_SCT_CLOCK_IS_THE): The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 2 (THE_INPUT_SELECTED_B): The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 3 (RESERVED): Reserved.This is not reserved on the LPC15xx. Need to add back in from spec. |
| CKSEL | SCT clock select 0 (RISING_EDGES_ON_INPU): Rising edges on input 0. 1 (FALLING_EDGES_ON_INP): Falling edges on input 0. 2 (RISING_EDGES_ON_INPU): Rising edges on input 1. 3 (FALLING_EDGES_ON_INP): Falling edges on input 1. 4 (RISING_EDGES_ON_INPU): Rising edges on input 2. 5 (FALLING_EDGES_ON_INP): Falling edges on input 2. 6 (RISING_EDGES_ON_INPU): Rising edges on input 3. 7 (FALLING_EDGES_ON_INP): Falling edges on input 3. |
| NORELAOD_L | A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. |
| NORELOAD_H | A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. |
| INSYNC | Synchronization for input N (bit 9 = input 0, bit 10 = input 1,…, bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. |
| AUTOLIMIT_L | A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. |
| AUTOLIMIT_H | A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. |
| RESERVED | Reserved |